A digital to analog converter (DAC) converts a digital input data word comprising several data bits and outputs an analog output which is proportional to the value of the input binary data word. The analog output signal is e.g. a current, a voltage, a charge or an analog signal or a frequency proportional to the value of the input data word.
An ideal digital to analog converter has an input-output characteristic which is a straight line through the origin as can be seen in FIG. 1. In the digital to analog converter (DAC) according to the state of the art, the actual input-output characteristic is a line which deviates from the ideal straight line, i.e. the input-output characteristic of the conventional digital to analog converter according to the state of the art is a non-linear input-output characteristic. The non-linearity of the input-output characteristic of the conventional digital to analog converter is due to offset and gain errors. Digital to analog converters are integrated circuits which are in most cases implemented as digital to analog converters having an array of cell elements which actually perform the conversion from the digital value to the analog signal. These cell array elements comprise a plurality of cell elements, such as current sources, capacitors, resistors, which are switched by means of switches controlled by the digital input data to be converted. A digital to analog converter (DAC) having a cell array consisting of current sources is designated as a current switch digital to analog converter a (DAC) comprising a cell array of resistor elements is referred to as a resistor string digital to analog converter, and a digital to analog converter (DAC) having a cell array consisting of capacitors and is referred to as a charge redistribution digital to analog converter.
Depending on the application of the digital to analog converter, the cell array is organized substantially in three different possible ways, i.e. as a binary-weighted array, as a thermometric array or as a mixed array.
In the binary-weighted cell array, the dimension of the cell elements goes as the power of two. In a thermometric cell array, all cell elements have the same dimension. In a mixed cell array, a part of the array is thermometer-coded, and the other part of the cell array is binary-coded.
In practical integrated circuits, a mismatch among the cell elements within the cell array of a digital to analog converter exists. The mismatch, i.e. the difference between the actual physical property of the cell element and the nominal property value of the cell element, can occur for several reasons.
The first cause for the mismatch is that the wafer manufacturing process is not completely homogeneous over the whole wafer surface. As a consequence of the inhomogeneous wafer manufacturing process nominal identical cell elements which are placed on the wafer at a certain distance from each other actually show a different physical behavior. The closer the cell elements are located to each other, the lower is the mismatch between both cell elements. For this reason, it is common practice to limit the extension of the wafer area on which the cell elements of the cell array are placed. This is usually accomplished by organizing the cell elements on the wafer in a bidimensional array structure. The non-homogenity of the manufacturing process on the surface of the wafer leads to the presence of a gradient in the physical behavior of the cell elements. This means that a given physical property of the cell elements deviates from its nominal value in a more or less linear fashion along a given direction on the wafer.
In FIG. 2 a mismatch of cell elements integrated on a wafer is modeled as a bidimensional Gaussian function of the distance from the center of the cell array, wherein the mismatch is shown as a bend surface on the top part of the picture. The normalized mismatch is normalized with respect to a reference value R0, such as R1/R0, wherein R0 is a reference resistance value of a cell element at the center of the cell array.
Another source of mismatch among cell elements leading to a distribution as shown in FIG. 2 is the so-called “border proximity effect”. In an integrated circuit, the physical property of a cell element, such as a resistor, a capacitor or a transistor, depends also on the silicon structures implemented close to it. In a bidimensional array of cell elements those cell elements which are close to the border of the cell array have a “local” silicon structure which is different from the silicon structure of the cell elements close to the center of the cell array. This causes a mismatch in the physical behavior of the cell elements. This mismatch is mainly a function of the distance of the cell element from the center of the cell array, as can be seen in FIG. 3. A digital to analog converter (DAC) comprising a cell array as shown in FIG. 3 shows a non-linearity of this input-output characteristic, wherein the non-linearity depends on how the cell array elements are connected to each other in a wiring pattern.
FIG. 3 shows a cell array having a plurality of cell elements integrated on a wafer in a bidimensional cell matrix. In the example shown in FIG. 3, the cell matrix comprises 8×8 cell elements wherein each cell element can be a resistor, a capacitor, a transistor, a current source or a diode. The mismatch distribution is circular symmetric as can be seen in FIG. 3.
FIG. 4 shows a wiring or scanning pattern for connecting the cell elements of a cell array in series according to the state of the art. The usual way of scanning or wiring a thermometer-coded digital to analog converter is performed by scanning the cell array line per line as shown in FIG. 4.
The disadvantage of this conventional wiring pattern is that, in the presence of border proximity effects, the integral or accumulated non-linearity of the digital to analog converter is high. Because the cell array is scanned line-wise the cell elements with a higher mismatch, i.e. the cell elements in row 8, as show in FIG. 4, are summed one after the other right at the beginning of the wiring or scanning sequence. Therefore, the mismatch is accumulated. By using a cell array having the wiring pattern as shown in FIG. 4, the digital to analog converter has an increased non-linearity of the input-output characteristic.
Accordingly, it is the object of the present invention to provide a cell array which has a reduced accumulated mismatch.